04-Sequential_Logic_Design

I Introduction

I.1 Trigger

• Level-triggered/sensitive
  • Output controlled by the level of the clock input.
• Edge-triggered/sensitive
  • Output changes only at the point in time when the clock changes from value to the other.
  • Can be positive-edge triggered (0 to 1), or negative-edge triggered (1 to 0).

Flip-flops（触发器） are edge-triggered while clocked (gated) latches（锁存器） are level-sensitive.

I.2 Implement

I.3 Types of Sequential Circuits

实验指导——初始化

II Analysis

II.1 Finite State Machine

II.1.1 State Diagram

II.1.2 State Table

II.2 Basic Analysis Procedure

The analysis consists of obtaining a suitable description that demonstrates the time sequence of inputs, outputs, and states.

II.2.1 example

下面所表示的信息是一致的

III Basic sequential logic elements

III.1 Latch

III.1.1 simple one

下面是最为简单的双稳态电路，该电路没有输入，有两个输出 $Q\bar{Q}$

没有输入也就意味着不能够控制该电路

还存在亚稳态（老师上课提了一嘴）

III.1.2 SR Latch

III.1.2.1 analysis

III.1.2.2 summery

III.1.2.2.1 SR Latch with NOR Gates

III.1.2.2.2 $\overline{SR}$ Latch with NAND Gates

III.1.2.3 SR Latch with Control Input

III.1.3 Latch

在 SR Latch with NOR Gates 中，我们发现不应该出现 $\{\begin{array}{l}S=1\\ R=1\end{array}$ 的情况，而 $\{\begin{array}{l}S=0\\ R=0\end{array}$ 的情况可以被取代，所以我们直接将一个输入（D,data）取其本身和取非即可，再使用输入 C 进行控制，就形成了 D latch

III.1.3.1 The Latch Timing Problem

III.2 Flip-Flop

III.2.1 Flip-Flop

III.2.1.1 Implement

也就是说一定要 C 取 1 后再取 0 信号才能顺利传递；可以看到信号向右传是在 C 由 1 变为 0 的时候发生的，也就是说这是 下降沿触发的 (negative-edge triggered flip-flop)

• 时钟上升沿
• D 的值发生了变化

III.2.1.1.1 Latch vs. D Flip-Flop

我们在前面就已经谈到了二者的区别

我们可以通过仿真波形图来比较直观地对比二者

III.2.1.1.2 problem

当然依旧存在 问题：

• 延迟高，电路效率低
• （没太搞懂）
  解决 办法： 使用 edge-triggering flip-flop

III.2.1.2 Enabled D Flip-Flop

III.2.1.3 Resettable D Flip-Flop

III.2.2 JK Flip-Flop

III.2.2.1 Implement

III.2.3 T Flip-Flop

IV Sequential logic design

IV.1 Some definitions

IV.1.1 Equivalent State

• Two states are equivalent if their response for each possible input sequence is an identical output sequence.
• Alternatively, two states are equivalent if their outputs produced for each input symbol is identical and their next states for each input symbol are the same or equivalent.

IV.1.1.1 example

IV.1.2 Moore and Mealy Models

在上面的 Introduction 中我们简单介绍了 Moore and Mealy Models，下面是其一对例子：

在 Moore 中，输出只受当前状态影响，但是下一状态还是可以受到输入的影响

IV.2 The design procedure

到 这里 都直接跳过了，期末再来复习罢

V Classic sequential logic elements

V.1 Registers

V.1.1 Basic introduction

V.1.1.1 2-bit Register

V.1.1.2 4-Bit Register: Clock Gating

V.1.2 Registers in the digital system

V.1.2.1 Retister Transfers

V.1.2.2 Register Representation

来自 lec04-3 p14，为什么在 $K_1$ 下降沿才发生 transfer ？

V.1.2.3 Register Transfer Structures

V.1.2.3.1 overview

• Multiplexer-Based Transfers - Multiple inputs are selected by a multiplexer dedicated to the register, e.g.,
  • Shift registers
  • Counters
• Bus-Based Transfers - Multiple inputs are selected by a shared multiplexer driving a bus that feeds inputs to multiple registers
• Three-State Bus - Multiple inputs are selected by 3-state drivers with outputs connected to a bus that feeds multiple registers
• Other Transfer Structures - Use multiple multiplexers, multiple buses, and combinations of all the above

V.1.2.3.2 Dedicated Multiplexers vs. Single Bus

V.1.2.3.3 Multiplexer Bus vs. 3-State Bus

V.1.3 Shift Registers

V.1.3.1 Shift Register with Parallel Load

以第一个或门对应的电路部分为例，真值表如下（后面有时间再自己画表格）：

用 $X_0$ 表示输出，Functionality 表示功能，可以看到：

• hold 表示保持值不变
• parallel load 表示成功将数值直接放入对应寄存器中
• serial load 表示将上一个的数值放入对应寄存器中，从而实现了 移位 的目的

实验指导——移位寄存器

V.2 Counters

V.2.1 Basic introduction

• Programs consist of a list of instructions that are to be executed one after another (for the most part).
• The PC keeps track of the instruction currently being executed.
• The PC increments once on each clock cycle, and the next program instruction is then executed.
  

V.2.2 Ripple Counters

V.2.3 Synchronous Counters

V.2.4 Other Counters

• Divide-by-n (Modulo n) Counter
• BCD counter with D flip-flops

实验指导——计数器
对于 BCD 在 lec04-3 的 34 页后没看了，如果不懂了再看